datasheet low skew 2 input mux and 1 to 8 clock buffer ics552-02 idt? / ics? low skew 2 input mux and 1 to 8 clock buffer 1 ics552-02 rev l 051310 description the ics552-02 is a low skew, single-input to eight- output clock buffer. the device offers a dual input with pin select for switching between two clock sources. it is part of idt?s clockblocks tm family. see the ics553 for a 1 to 4 low skew buffer. for more than 8 outputs s ee the mk74cbxxx buffalo tm series of clock drivers. idt makes many non-pll and pll based low skew output devices as well as zero delay buffers to synchronize clocks. contact us for all of your cloc king needs. features ? extremely low skew outputs (50ps maximum) ? packaged in 16 pin tssop ? pb (lead) free package ? low power cmos technology ? operating voltages of 2.5 v to 5 v ? output enable pin tri-states outputs ? 5 v tolerant input clocks ? input/output clock frequency up to 200 mhz ? input clock multiplexer simplifies clock selection ? industrial temperature block diagram o e q 3 q 4 q 2 q 5 q 6 q 1 q 0 q 7 in a in b 10 s e la
ics552-02 low skew 2 input mux and 1 to 8 clock buffer clock mux and buffer idt? / ics? low skew 2 input mux and 1 to 8 clock buffer 2 ics552-02 rev l 051310 pin assignment input source select pin descriptions external components a minimum number of external components are require d for proper operation. decoupling capacitors of 0.01 f should be connected between vdd on pin 2 and gnd on pin 7, and between vdd on pin 15 and gnd on pin 10, as close to the device as possible. a 33 series terminating resistor should be used on each clock output if the trace is longer than 1 inc h. to achieve the low output skews that the ics552-02 is capable of, careful attention must be paid to bo ard layout. essentially, all 8 outputs must have identi cal terminations, identical loads, and identical tr ace geometries. if they do not, the output skew will be degraded. for example, using a 30 series termination on one output (with 33 on the others) will cause at least 15ps of skew. 12 1 11 2 10 3 9 oe 4 vdd 5 q0 6 vdd 7 q1 8 q2 q7 q6 q5 q3 q4 ina gnd gnd 16 15 14 13 inb sela 16 pin tssop sela input 0 inb 1 ina pin number pin name pin type pin description 1 oe input output enable. tri-states outputs when low. internal pull-up resistor. 2 vdd power connect to +2.5v, +3.3v or +5.0v. must be the same as pin 15. 3 q0 output clock output 0 4 q1 output clock output 1 5 q2 output clock output 2 6 q3 output clock output 3 7 gnd power connect to ground. 8 inb input clock input b. 5v tolerant input. 9 ina input clock input a. 5v tolerant input. 10 gnd power connect to ground. 11 q4 output clock output 4 12 q5 output clock output 5 13 q6 output clock output 6 14 q7 output clock output 7 15 vdd power connect to + 2.5v, +3.3v or +5.0v. must b e the same as pin 2. 16 sela input selects either ina or inb. internal pull -up resistor.
ics552-02 low skew 2 input mux and 1 to 8 clock buffer clock mux and buffer idt? / ics? low skew 2 input mux and 1 to 8 clock buffer 3 ics552-02 rev l 051310 absolute maximum ratings stresses above the ratings listed below can cause p ermanent damage to the ics552-02. these ratings, which are standard values for idt commercially rate d parts, are stress ratings only. functional operat ion of the device at these or any other conditions above t hose indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters a re guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics vdd=2.5 v 5% , ambient temperature -40 to +85 c, unless stated otherwise item rating supply voltage, vdd 7 v sela, oe, and all outputs -0.5 v to vdd+0.5 v ina and inb -0.5v to 5.5v ambient operating temperature -40 to +85 c storage temperature -65 to +150 c junction temperature 175 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature -40 ? +85 c power supply voltage (measured in respect to gnd) +2 .375 +5.25 v parameter symbol conditions min. typ. max. units operating voltage vdd 2.375 2.625 v input high voltage, ina, inb v ih note 1 vdd/2+0.5 5.5 v input low voltage, ina, inb v il note 1 vdd/2-0.5 v input high voltage, oe, sela v ih 1.8 vdd v input low voltage, oe, sela v il 0.7 v output high voltage v oh i oh = -16 ma 2 v output low voltage v ol i ol = 16 ma 0.4 v operating supply current idd no load, 135 mhz 35 ma short circuit current i os each output 60 ma
ics552-02 low skew 2 input mux and 1 to 8 clock buffer clock mux and buffer idt? / ics? low skew 2 input mux and 1 to 8 clock buffer 4 ics552-02 rev l 051310 dc electrical characteristics (continued) vdd=3.3 v 5% , ambient temperature -40 to +85 c, unless stated otherwise vdd=5 v 5% , ambient temperature -40 to +85 c, unless stated otherwise note: 1. nominal switching threshold is vdd/2 parameter symbol conditions min. typ. max. units operating voltage vdd 3.135 3.465 v input high voltage, ina, inb v ih note 1 vdd/2+0.7 5.5 v input low voltage, ina, inb v il note 1 vdd/2-0.7 v input high voltage, oe, sela v ih 2 vdd v input low voltage, oe, sela v il 0.8 v output high voltage v oh i oh = -25 ma 2.4 v output low voltage v ol i oh = 25 ma 0.4 v output high voltage (cmos level) v oh i oh = -12 ma vdd-0.4 v operating supply current idd no load, 135 mhz 50 ma short circuit current i os each output 80 ma parameter symbol conditions min. typ. max. units operating voltage vdd 4.75 5.25 v input high voltage, ina, inb v ih note 1 vdd/2+1 5.5 v input low voltage, ina, inb v il note 1 vdd/2-1 v input high voltage, oe, sela v ih 2 vdd v input low voltage, oe, sela v il 0.8 v output high voltage v oh i oh = -35 ma 2.4 v output low voltage v ol i ol = 35 ma 0.4 v output high voltage (cmos level) v oh i oh = -12 ma vdd-0.4 v operating supply current idd no load, 135 mhz 85 ma short circuit current i os each output 100 ma
ics552-02 low skew 2 input mux and 1 to 8 clock buffer clock mux and buffer idt? / ics? low skew 2 input mux and 1 to 8 clock buffer 5 ics552-02 rev l 051310 ac electrical characteristics vdd = 2.5v 5% , ambient temperature -40 to +85 c, unless stated otherwise vdd = 3.3v 5% , ambient temperature -40 to +85 c, unless stated otherwise vdd = 5.0v 5% , ambient temperature -40 to +85 c, unless stated otherwise notes: 1. with rail-to-rail input clock. 2. between any two outputs with equal loading. 3. propagation delay matching through the part. 4. duty cycle on outputs will match incoming clock duty cycle. consult idt for tight duty cycle clock generators. parameter symbol conditions min. typ. max. units input frequency 0 200 mhz output rise time t or 0.8 to 2.0 v, c l =15 pf 1.0 1.5 ns output fall time t of 2.0 to 0.8 v, c l =15 pf 1.0 1.5 ns propagation delay note 1 3.5 ns output to output skew note 2 rising edges at vdd/2 0 50 ps input a to input b skew note 3 0 50 ps parameter symbol conditions min. typ. max. units input frequency 0 200 mhz output rise time t or 0.8 to 2.0 v, c l =15 pf 0.6 1.0 ns output fall time t of 2.0 to 0.8 v, c l =15 pf 0.6 1.0 ns propagation delay note 1 2.0 3.0 5.5 ns output to output skew note 2 rising edges at vdd/2 0 50 ps input a to input b skew note 3 0 50 ps part to part skew 3.5 ns parameter symbol conditions min. typ. max. units input frequency 0 200 mhz output rise time t or 0.8 to 2.0 v, c l =15 pf 0.3 0.7 ns output fall time t of 2.0 to 0.8 v, c l =15 pf 0.3 0.7 ns propagation delay note 1 2.8 ns output to output skew note 2 rising edges at vdd/2 0 50 ps input a to input b skew note 3 0 50 ps
ics552-02 low skew 2 input mux and 1 to 8 clock buffer clock mux and buffer idt? / ics? low skew 2 input mux and 1 to 8 clock buffer 6 ics552-02 rev l 051310 package outline and package dimensions (16 pin tssop, 4.40 mm body, 0.65 mm pitch) package dimensions are kept current with jedec publ ication no. 95, mo-153 ordering information ?ln? suffix to the part number are the pb-free conf iguration and are rohs compliant. while the information presented herein has been che cked for both accuracy and reliability, integrated device technology (idt) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licens es are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliabil ity, or other extraordinary environmental requirements are not recommended with out additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt doe s not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 552G-02ILN 552g02in tubes 16-pin tssop -40 to +85 c 552G-02ILNt 552g02in tape and reel 16-pin tssop -40 to +85 c in d ex ar ea 1 2 16 d e1 e s e a t in g p lan e a 1 a a 2 e - c - b aaa c c l millimeters inches symbol min max min max a -- 1.20 -- 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 0 8 0 8 aaa -- 0.10 -- 0.004
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